VHDL Packages

Posted in S3BOARD, VHDL, Xilinx on 2011-08-04 at 17:46:18 by Chris – 9 Comments

In my efforts to make my code more modular and testable, I've been playing with VHDL packages. This came about because I was building a logic block that would do different things depending on the value of its "operation" input. Since there is a well-defined set of supported operations, an enumerated type makes sense, but how can an enumerated type be exported so it may be used by "clients"? Previously I've only declared enumerated types as the type of a state machine, all of which have been confined to a single file.

My solution is straightforward, if not particularly elegant (if you know a better way please tell me!). I made a simple proof-of-concept for it, using just a simple gate entity which implements a logic function (OP_AND or OP_OR) which is user-selectable. First declare a package with a definition for the user-defined type for Operation:

-- gate_pkg.vhdl
library ieee;

package gate_pkg is
    type Operation is (
        OP_AND,
        OP_OR
    );
end package;

Then define and implement the gate entity:

-- gate.vhdl
library ieee;

use ieee.std_logic_1164.all;
use work.gate_pkg.all;

entity gate is
    port(
        op_in : in Operation;
        a_in  : in std_logic;
        b_in  : in std_logic;
        x_out : out std_logic
    );
end entity;

architecture rtl of gate is
begin
    x_out <=
        a_in or b_in when op_in = OP_OR else
        a_in and b_in when op_in = OP_AND;
end architecture;

And finally you can import the package and use its types and its logic blocks:

-- toplevel.vhdl
library ieee;

use ieee.std_logic_1164.all;
use work.gate_pkg.all;

entity toplevel is
    port(
        op_in : in std_logic;
        a_in  : in std_logic;
        b_in  : in std_logic;
        x_out : out std_logic
    );
end entity;

architecture structural of toplevel is
    signal op : Operation;
begin
    u1: gate
        port map(
            op_in => op,
            a_in  => a_in,
            b_in  => b_in,
            x_out => x_out
        );
    op <=
        OP_AND when op_in = '1' else
        OP_OR;
end architecture;

I have checked a fully-working example of this into GitHub. I also updated the GHDL simulation stuff I talked about in this blog post to use a .ghw file rather than a .vcd file for the waves. This means you can see the symbolic value of the enumerated type in GTKWave:

If you have a Digilent S3BOARD you can load it with the .bit file generated by the build. Button 3 sets the operation (OP_OR or OP_AND), button 2 and 1 set the inputs and LED 0 displays the output.

9 Comments

Why are you bothering to use components when direct instantiation is much more useful?

Reply

I wasn't aware that you could include type declarations (e.g the Operation type from the package described above) when doing direct instantiations. Can you point me to the syntax?

Reply

Like this:

-- toplevel.vhdl
library ieee;

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gate_pkg.all;

architecture behavioural of toplevel is
    signal op : Operation;
begin
    u1: entity work.gate
        port map(
            op_in => op,
            a_in => a_in,
            b_in => b_in,
            x_out => x_out
        );
    op <=
        OP_AND when op_in = '1'; else
        OP_OR;
end architecture;
Reply

Great, thanks for this. I have updated the code in GitHub and the description in the body of the post.

In the toplevel.vhdl, you have declared as below to be able to use the package,

use work.gate_pkg.all;

What does "work" stand for? Does that have any meaning or can I use any name I want?

Reply

Hi Nilesh,

The work identifier is a placeholder for the name of the current library, just like on Unix, $HOME is a placeholder for the current user's home directory. So "use work.gate_pkg.all" means, "look for gate_pkg in the same VHDL library as I'm in". Think of it as similar to this in C++ or Java. It's an identifier, but it should really be thought of as a reserved word, because creating an actual library called work will lead to all manner of confusion. See here for more information.

Chris

Reply

siwar dammak says:

2013-07-11 at 15:45:17 UTC

hello
I have a list of programme vhdl and I want to use its in only one programme
So how make it ?
thanks

Reply

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