MakeStuff

Nanduino » JTAG

NanduinoJTAG is a USB JTAG dongle implemented with a Nanduino board and some supporting software. If you're not familiar with JTAG, have a look at this site.

Currently it only supports the ATmega162 used in the S-AVR and the Xilinx XC9572 CPLD as target devices. I will add more devices incrementally. For programming the AVR it is extremely fast, programming and verifying the micro's 16 kbytes of flash in ~500ms. You can download the software from github, and build it on Windows or Linux according to this blog post. You can then query the JTAG chain like this:

> sudo host/nj
NanduinoJTAG Copyright (C) 2010 Chris McClelland
Found 2 devices in the JTAG chain:
  Device 0 (IDCODE=0x7940403F): ATMEL ATMEGA162 (rev H)
  Device 1 (IDCODE=0x29504093): XILINX XC9572 (rev C)

The nj program supports a bunch of options:

> sudo host/nj --help
NanduinoJTAG Copyright (C) 2010 Chris McClelland
Usage: nj [-eh] [-d <num>] [-f <fuses>] [-i <inFile>] [-o <outFile>]

Interact with NanduinoJTAG.

  -d, --device=<num>     target device
  -e, --erase            erase the flash, lock bits & maybe EEPROM
  -f, --fuses=<fuses>    set fuses (EX:HI:LO:LK)
  -i, --load=<inFile>    load flash from file
  -o, --save=<outFile>   save flash to file
  -h, --help             print this help and exit

Program an ATmega162

To load the example S-AVR firmware described here:

> mkdir simple
> cd simple
> wget http://www.swaton.ukfsn.org/uploads/2009/01/Makefile
> wget http://www.swaton.ukfsn.org/uploads/2009/01/main.c
> make
> cp firmware.hex ..
> cd ..
> sudo host/nj --device=0 --erase --load=firmware.hex
NanduinoJTAG Copyright (C) 2010 Chris McClelland
Found one device in the JTAG chain:
  Device 0 (IDCODE=0x7940403F): ATMEL ATMEGA162 (rev H)
Fuses = 0xFF99FFFF (EX:HI:LO:LK)
Erasing chip...
Programming Atmel chip using HEX file firmware.hex...
Load operation completed with returncode 0x00000000, numfails=0

Program an XC9572

Have a look at the VHDL in the test000 subproject of this git repo:

entity test is
    Port ( a : in  STD_LOGIC;
        b : in  STD_LOGIC;
        x : out  STD_LOGIC);
end test;

architecture test_arch of test is
begin
    x <= not a and not b;
end test_arch;

The pin assignments of a, b and x are defined in the corresponding ucf file:

NET a LOC=P1;
NET b LOC=P2;
NET x LOC=P3;

In the above pic, input pins 1 and 2 of the CPLD are connected to the least significant two bits of port A, the one driven by the counter program I loaded previously. The CPLD's output on pin 3 is connected to an LED. The result is that the LED lights when both PA0 and PA1 lines from the micro are low. This condition is true immediately after reset, for one second, followed by three seconds where it is no longer true, and so on, a square wave with a 25% duty cycle.

Install Xilinx ISE WebPack and build it as described in the README. The first time you build, it's important to do it from within the WebPack GUI. The XSVF file generated by the Makefile is intended specifically for the JTAG chain you see in the above picture. It's a chain of two devices, the first being an Atmel ATmega162 microcontroller and the second being a Xilinx XC9572 CPLD. If your chain is different, you will need to change either the design or the impact.batch file.

> make flash
impact -batch impact.batch
Release 11.4 - iMPACT L.68 (nt)
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
:
..\..\apps\nanduinoJtag\host\Debug\nj --load=test.xsvf
NanduinoJTAG Copyright (C) 2010 Chris McClelland
Found 2 devices in the JTAG chain:
  Device 0 (IDCODE=0x7940403F): ATMEL ATMEGA162 (rev H)
  Device 1 (IDCODE=0x29504093): XILINX XC9572 (rev C)
Playing XSVF file test.xsvf...
Load operation completed with returncode 0x00000000, numfails=0

How Does It Work?

JTAG defines four signals:

Signal	Description	Port	Port Direction
TCK	Test Clock	PB7	OUT
TMS	Test Mode Select	PB6	OUT
TDO	Test Data Output	PB5	IN
TDI	Test Data Input	PB4	OUT

The signals are named from the point of view of the target device. For example the TDO signal is an output on the target device; it drives the Nanduino's PB5 line, which must therefore be configured as an input:

Each JTAG target device incorporates a sixteen-state finite state machine called the TAP controller:

The state machine transitions according to the level of TMS at the rising edge of TCK. Some states allow data to be clocked into (and simultaneously out of) the target device using the TDO and TDI signals. There are a basic set of operations supported by all JTAG-capable devices, but to do any serious work you need to delve into the device-specific JTAG implementation documentation. For AVR microcontrollers this is described in the data sheets, and describes how to read & write the device's flash, fuses & EEPROM, and more advanced stuff like setting breakpoints and reading the device state.

This is all implemented in the NanduinoJTAG firmware. Each operation is triggered by a set of custom USB commands implemented by the NanduinoJTAG using LUFA. The host-side code interacts with the NanduinoJTAG using LibUSB.