MakeStuff

It has been a long time since I put any thought into version 2 of my USB MegaDrive DevKit. I'm currently putting together a prototype based on a Digilent Nexys2 FPGA board. So far I have managed to:

• Power the Nexys2 from the MegaDrive's 5V supply.
• Buffer the MegaDrive's 7.6MHz clock using this board.
• Verify that the MegaDrive's clock is actually running at the expected rate (0x73F9XX ~ 7.6004MHz).
• Use one of the Digital Clock Managers on the FPGA to multiply the 7.6MHz clock by 14 to give 106.4MHz.
• Use this 106.4MHz to clock a memory controller state machine, running the on-board CellularRAM at half that frequency.
• Fix up the host interface reference design to eliminate the need to force FSM encoding.
• Benchmark block writes using the Adept tool over USB to the CellularRAM at 3.94Mbyte/s.
• Use a transistor switch to give the FPGA control of the MegaDrive's RESET line.

This 0x73F9 is the top 16 bits of a 24-bit counter giving MegaDrive clocks per second: 0x73F9XX ~ 7.6004MHz

Still to do on this prototype:

• Build a MegaDrive cartridge PCB with an FX2-100S-1.27SV(71) edge connector for interfacing with the Nexys2.
• Implement the 68000 bus reads and writes in the VHDL.
• Build the SD-card interface PCB and write the VHDL for a DMA controller clocking the SD card in SPI mode at ~25MHz.
• Optimise the memory controller to use burst writes of data from the host - this should increase throughput to ~5Mbyte/s.

If you want to look at the VHDL for the host interface and the memory controller, you can download it under a GPLv3 licence from here.

This entry was posted on Sunday, July 11th, 2010 at 15:37:29 UTC and is filed under Electronics. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.